A radio frequency (RF) power amplifier, for example of a transmitter in a wireless communications system, typically includes interconnected transistor circuits for amplifying a RF signal to a high power level. The amplified RF signal could then be transmitted into space via an antenna.
Modern wireless communications systems relay on the use of complex digital modulation schemes and multiple carriers to fulfill the requirements of high data transmission capacity over a minimal frequency spectrum. As a consequence, the amplified RF signal to be transmitted and received has usually a complex and strongly time-varying envelope. This complex signal behavior may result in different forms of distortion, including adjacent and alternate channel distortion and intermodulation distortion (IMD). For digital communications system IMD is a large problem since IMD products can be interpreted by the digital system as payload signals. Thus, stringent linearity requirements are imposed on the RF power amplifier and its including elements to suppress the IMD products. A commonly applied technique to improve the linearity of the power amplifier is to apply a biasing signal so that the transistors of the amplifier are caused to operate in a more linear portion of their available operation range.
A possible prior art solution for generating the biasing signal is to directly detect the power of an input RF signal of the amplifier and generate the biasing signal based thereon. However, such solutions are very complex and require digital signal processors, thereby increasing the complexity and the cost of the amplifier.
U.S. Pat. No. 5,757,237 discloses a power amplifier that includes two cascaded MESFETs (metal semiconductor field effect transistors) and a dynamic biasing circuit. This dynamic biasing circuit in turn comprises a sampling circuit and a voltage summing circuit. An input RF signal is provided to the gate electrode of the first MESFET, which outputs an intermediate AC (alternating current) signal at its drain electrode. This AC signal is brought through an impedance matching element to the gate of the second MESFET. An output RF signal is then provided at the drain of this second MESFET. The sampling circuit is connected to the drain electrode of the first MESFET for detecting the amplitude of an envelope of the intermediate AC signal. Based on this AC signal a bias adjusting signal is generated by the sampling circuit and is provided to the summing circuit. This summing circuit is also connected to a fixed bias voltage source. The bias adjusting signal from the sampling circuit is then used to modulate the fixed DC voltage signal from this voltage source in order to generate a dynamic biasing signal. This resulting biasing signal is applied to the gate electrode of the second MESFET.
A major problem with the dynamic biasing solution presented by U.S. Pat. No. 5,757,237 is the operation of the sampling circuit. Detection of the amplitude of the envelope the intermediate AC signal requires a very fast sampling circuitry solution. In particular for detecting RF signals with a frequency in the order of 100 MHz or GHz and creating a bias adjusting signal therefrom is extremely difficult and almost next to impossible. As a consequence the biasing circuit of U.S. Pat. No. 5,757,237 is not suitable for usage with the high-frequency RF signals of modern wireless communications systems.